1. Field of the Invention
The present invention relates to an apparatus for controlling a card device and a clock control method.
2. Description of the Related Art
Electronic equipment such as a personal computer, a PDA, a cellular phone, and a digital camera often employs a removable storage device. Recently an SD memory card has frequently been used as a removable storage device. The SD memory card includes a flash memory and meets the demand for miniaturization, high-speed data processing, optimization of storage capacity, etc.
Electronic equipment mounted with an SD memory card includes an SD memory card host controller (referred to as a host controller hereinafter) for controlling the SD memory card. The host controller supplies a clock to the SD memory card via an SD bus to communicate with the SD memory card.
In order to reduce power consumption, the host controller usually stops supplying a clock to the SD memory card when no access is gained to the SD memory card and no SD memory card is inserted. The host controller supplies a clock to the SD memory card when access to the SD memory card is required. This control is performed using a register included in the host controller.
The host controller writes data indicative of clock-on to an internal register to supply a clock (SDCLK) to the SD memory card and issue a read command. Then, a response (command response) to the read command is returned from the SD memory card. Latency (several tens of microseconds) of read data elapses from the receipt of the response to the start of data transfer (data cycle). After the data cycle has completed, the host controller writes data indicative of clock-off to the internal register to stop supplying the clock (SDCLK) to the SD memory card.
The SD memory card includes a PLL (phase locked loop) circuit. It can therefore perform a read operation without any trouble even when no clock is supplied from the SD bus during the above latency. Power consumption will therefore be wasted if a clock is supplied to the SD memory card during the latency.
Jpn. Pat. Appln. KOKAI Publication No. 9-204769 discloses a method of reducing power consumption of a memory card. However, it does not disclose reducing any power consumption on the host controller side.
Jpn. Pat. Appln. KOKAI Publication No. 2000-251464 discloses a method of selectively using one from among different clocks. However, it does not disclose stopping the supply of a clock during the latency of read data.